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ML145162
60 MHz and 85 MHz Universal Programmable Dual PLL Frequency Synthesizers
CMOS
Legacy Device: Motorola MC145162
The ML145162 is a dual phase-locked loop (PLL) frequency synthesizer especially designed for CT-1 cordless phone applications worldwide. This frequency synthesizer is also for any product with a frequency operation at 60MHz or below. The device features fully programmable receive, transmit, reference, and auxiliary reference counters accessed through an MCU serial interface. This feature allows this device to operate in any CT-1 cordless phone application. The device consists of two independent phase detectors for transmit and receive loops. A common reference oscillator, driving two independent reference frequency counters, provides independent reference frequencies for transmit and receive loops. The auxiliary reference counter allows the user to select an additional reference frequency for receive and transmit loops if required. * * * * * * * * * * * * * Operating Voltage Range: 2.5 to 5.5 V Operating Temperature Range: TA = - 40 to +75C Operating Power Consumption: 3.0 mA @ 2.5 V Maximum Operating Frequency: 60 MHz @ 200 mV p-p, VDD = 2.5 V Three or Four Pins Used for Serial MCU Interface Built-In MCU Clock Output with Frequency of Reference Oscillator /3//4 Power Saving Mode Controlled by MCU Lock Detect Signal On-Chip Reference Oscillator Supports External Crystals to 16.0 MHz Reference Frequency Counter Division Range: 16 to 4095 Auxiliary Reference Frequency Counter Division Range: 16 to 16,383 Transmit Counter Division Range: 16 to 65,535 Receive Counter Division Range: 16 to 65,535
P DIP 16 = EP PLASTIC DIP CASE 648
1
16
16 1
SOG 16 = -5P SOG PACKAGE CASE 751B
CROSS REFERENCE/ORDERING INFORMATION PACKAGE LANSDALE MOTOROLA P DIP 16 SOG 16 MC145162P MC145162D ML145162EP ML145162-5P
Note: Lansdale lead free (Pb) product, as it becomes available, will be identified by a part number prefix change from ML to MLE.
PIN ASSIGNMENT
CLK ADin Din ENB MCUCLK VSS OSCin OSCout 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 LD TxPDout fin-T TxPS/fTx VDD RxPS/FRx RxPDout fin-R
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BLOCK DIAGRAM
A 7 12-BIT PROGRAMMABLE REFERENCE COUNTER B C 25 8 OSCout 14-BIT PROGRAMMABLE AUXILIARY REFERENCE COUNTER D fR2 fR1
OSCin
4
MCUCLK
5
3/
4
12-BIT SHIFT REGISTER
14-BIT SHIFT REGISTER
TRANSMIT SELECT
Tx PHASE DETECTOR
15
TxPDout
ADin CLK Din ENB TxPS/fTx RxPS/fRx
2 1 3 4 13 11 16-BIT SHIFT REGISTER MCU INTERFACE PROGRAMMING MODE CONTROL CONTROL REGISTER
16
LD
fin-T
14
16-BIT Tx PROGRAMMABLE COUNTER
RECEIVE SELECT
Rx PHASE DETECTOR
10
RxPDout
16-BIT SHIFT REGISTER
fin-R
9
16-BIT Rx PROGRAMMABLE COUNTER
VDD = PIN 12 VSS = PIN 6
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MAXIMUM RATINGS* (Voltages Referenced to VSS)
Symbol VDD Vin Iin, Iout IDD, ISS Tstg Rating DC Supply Voltage Input Voltage, All Inputs DC Current Drain Per Pin DC Current Drain VDD or VSS Pins Storage Temperature Range Value - 0.5 to + 6.0 - 0.5 to VDD + 0.5 10 30 - 65 to + 150 Unit V V mA mA C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS (Vin or Vout) VDD. Unused pins must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open.
* Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the limits in the Electrical Characteristics tables or Pin Descriptions section.
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS, TA = 25C)
Guaranteed Limit Symbol VDD VOL VOH VIL VIH IOH IOL IIL Input Current (Vin = 0) Output Current (Vout = 2.2 V) (Vout = 5.0 V) (Vout = 0.3 V) (Vout = 0.5 V) Characteristic Power Supply Voltage Range Output Voltage (Iout = 0) (Vin = VDD or 0) Input Voltage (Vout = 0.5 V or VDD - 0.5 V) 0 Level 1 Level 0 Level 1 Level Source Sink OSCin, fin-T, fin-R ADin, CLK, Din, ENB IIH (Vin = VDD - 0.5) OSCin, fin-T, fin-R ADin, CLK, Din, ENB IOZ Cin Cout IDD(stdby) IDD Three-State Leakage Current (Vout = 0 V or 5.5 V) Input Capacitance Output Capacitance Standby Current (All Counters are in Power-Down Mode with Oscillator On) Operating Current ML145162: 200 mV p-p input at f in-T and fin-R = 60 MHz VDD -- 2.5 5.5 2.5 5.5 2.5 5.5 2.5 5.5 2.5 5.5 2.5 5.5 2.5 5.5 2.5 5.5 2.5 5.5 2.5 5.5 5.5 -- -- 2.5 5.5 2.5 Min 2.5 -- -- 2.45 5.45 -- -- 1.75 3.85 - 0.18 - 0.55 0.18 0.55 -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max 5.5 0.1 0.1 -- -- 0.75 1.65 -- -- -- -- -- -- - 30 - 66 - 1.0 - 1.0 30 66 5.0 5.0 100 8.0 8.0 0.3 1.5 3.0 nA pF pF mA mA A mA V Unit V V
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SWITCHING CHARACTERISTICS (TA = 25C, CL = 50 pF)
Symbol tTLH tTHL tr, tf tw fmax tst tsu th trec tsu1 th1 f fMCUCLK Output Rise Time Output Fall Time Input Rise and Fall Time Input Pulse Width Input Frequency Input = Sine Wave @ 200 mV p-p Minimum Start-Up Time Setup Time Hold Time Recovery Time Setup Time Hold Time Phase Detector Frequency Output Clock Frequency 3) (OSCin MCUCLK DATA to CLK ENB to CLK CLK to DATA ENB to CLK ENB to CLK CLK to ENB 5 5 5 4 4 2.5 5.5 3.0 5.0 3.0 5.0 2.5 - 5.5 2.5 - 5.5 100 200 80 40 80 40 80 600 dc dc OSCin CLK and ENB OSCin fin-R, fin-T Characteristic Figure No. 1 1 2 3 Guaranteed Limit VDD 2.5 5.5 2.5 5.5 2.5 5.5 2.5 5.5 2.5 - 5.5 2.5 - 5.5 Min -- -- -- -- -- -- 80 60 -- -- Max 200 100 200 100 5.0 4.0 -- -- 16 60 10 -- -- -- -- -- -- -- -- 12.5 5.33 Unit ns ns s ns MHz ms ns ns ns ns ns kHz MHz
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SWITCHING WAVEFORMS
tTLH ANY OUTPUT 90% 10% tTHL CLK, OSCin, fin-T, fin-R tr 90% 10% tf
Figure 1.
Figure 2.
tw ENB, CLK 50% ADin, Din 50% VSS tsu th VDD CLK VDD CLK FIRST CLK tsu1 ENB VSS LAST CLK th1 VSS ENB VDD PREVIOUS DATA LATCHED tsu 50% VSS 50% LAST CLK FIRST CLK trec VSS VDD
Figure 3.
VDD
Figure 4. ENB High During Serial Transfer
Figure 5. ENB Low During Serial Transfer
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PIN DESCRIPTIONS INPUT PINS OSCin/OSCout Reference Oscillator Input/Output (Pins 7, 8) These pins form a reference oscillator when connected to an external parallel-resonant crystal. Figure 6 shows the relationship of different crystal frequencies and reference frequencies for cordless phone applications in various countries. OSCin may also serve as input for an externally generated reference signal which is typically AC coupled. MCUCLK System Clock (Pin 5) This output pin provides a signal of the crystal frequency (OSCout) divided by 3 or 4 that is controlled by a bit in the control register. This signal can be a clock source for the MCU or other system clocks. ADin, Din, CLK, ENB Auxiliary Data In, Data In, Clock, Enable (Pins 2, 3, 1, 4) These four pins provide an MCU serial interface for programming the reference counter, the transmit-channel counter, and the receive-channel counter. They also provide various controls of the PLL including the power saving mode and the programming format. TxPS/fTx, RxPS/fRx Transmit Power Save, Receive Power Save (Pins 13, 11) For a normal application, these output pins provide the status of the internal power saving mode operation. If the transmit-channels counter circuitry is in power down mode, TxPS/fTx outputs a high state. If the receive-channels counter circuitry is in power down mode, RxPS/fRx is set high. These outputs can be applied for controlling the external power switch for the transmitter and the receiver to save MCU control pins. In the Tx/Rx channel counter test mode, the TxPS/fTx and RxPS/fRx pins output the divided value of the transmit channel counter (fTx) and the receive channel counter (fRx), respectively. This test mode operation is controlled by the control
register. Details of the counter test mode are in the Tx/Rx Channel Counter Test section of this data sheet. f in-T/f in-R Transmit/Receive Counter Inputs (Pins 14, 9) f in-T and f in-R are inputs to the transmit and the receive counters, respectively. These signals are typically driven from the loop VCO and AC coupled. The minimum input signal level is 200 mV p-p @ 60.0 MHz. OUTPUT PINS TxPDout/RxPDout Transmit/Receive Phase Detector Outputs (Pins 15, 10) These are three-state outputs of the transmit and receive phase detectors for use as loop error signals (see Figure 7 for phase detector output wave forms). Phase detector gain isVDD/4 volts per radian. Frequency fV > fR or fV leading: output = negative pulse. Frequency fV < fR or fV lagging: output = positive pulse. Frequency fV = fR and phase coincidence: output = high- impedance state. NOTE: fR is the divided-down reference frequency at the phase detector input and fV is the divided-down VCO frequency at the phase detector input. LD Lock Detect (Pin 16) The lock detect signal is associated with the transmit loop. The output at a high level indicates an out-of-lock condition (see Figure 7 for the LD output wave form). POWER SUPPLY VDD Positive Power Supply (Pin 12) VDD is the most positive power supply potential ranging from 2.5 to 5.5 V with respect to VSS. VSS Negative Power Supply (Pin 6) VSS is the most negative supply potential and is usually connected to ground.
A B C 25 D fR2 fR1
OSCin
N (12 BITS)
4
OSCout
M (14 BITS)
Crystal 11.150 MHz 11.150 MHz 10.240 MHz 12.000 MHz
N Value 446 223 512 600
fR1B 6.25 kHz 12.5 kHz 5.0 kHz 5.0 kHz
fR2C 1.0 kHz
Figure 6. Reference Frequencies for Cordless Phone Applications of Various Countries
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(OSCin
fR, REFERENCE REFERENCE COUNTER) fV, FEEDBACK (fin-T Tx COUNTER OR fin-R Rx COUNTER) TxPDout OR RxPDout LD
VH VL VH VL
*
VH HIGH IMPEDANCE
VH = High voltage level. VL = Low voltage level. *At this point, when both fR and fV are in phase, the output is forced to near mid supply. NOTE: The TxPDout and RxPDout generate error pulses during out-of-lock conditions. When locked in phase and frequency, the output is high impedance and the voltage at that pin is determined by the low-pass filter capacitor.
Figure 7. Phase Detector/Lock Detector Output Waveforms
MCU PROGRAMMING SCHEME The MCU programming scheme is defined in two formats controlled by the ENB input. If the enable signal is high during the serial data transfer, control register/reference frequency programming is selected. If the ENB is low, programming of the transmit and receive counters is selected. During programming of the transmit and receive counters, both ADin and Din pins can input the data to the transmit and receive counters. Both counters' data is clocked into the PLL internal shift register at the leading edge of the CLK signal. It is not necessary to reprogram the reference frequency counter/control register when using the enable signal to program the transmit/receive channels. In programming the control register/reference frequency scheme, the most significant bit (MSB) of the programming word identifies whether the input data is the control word or the reference frequency data word. If the MSB is 1, the input data is the control word (Figure 8). Also see Figure 8 and Table 1 for control register and bit function. If the MSB is 0, the input data is the reference frequency (Figure 9). The reference frequency data word is a 32-bit word containing the 12-bit reference frequency data, the 14-bit auxiliary reference frequency counter information, the reference frequency selection plus, the auxiliary reference frequency counter enable bit (Figure 9). If the AUX REF ENB bit is high, the 14-bit auxiliary reference frequency counter provides an additional phase reference frequency output for the loops. If AUX REF ENB bit is low, the auxiliary reference frequency counter is forced into
power-down mode for current saving. (Other power down modes are also provided through the control register per Table 2 and Figure 8.) At the falling edge of the ENB signal, the data is stored in the registers. There are two interfacing schemes for the universal channel mode: the three-pin and the four-pin interfacing schemes. The three-pin interfacing scheme is suited for use with the MCU SPI (serial peripheral interface) (Figure 10), while the four-pin interfacing scheme is commonly used for general I/O port connection (Figure 11). For the three-pin interfacing scheme, the auxiliary data select bit is set to 0. All 32 bits of data, which define both the16-bit transmit counter and the 16-bit receive counter, latch into the PLL internal register through the data in pins at the leading edge of CLK. See Figures 12 and 13. For the four-pin interfacing scheme, the auxiliary data select bit is set to 1. In this scheme, the 16-bit transmit counter's data enters into the ADin pin at the same time as the 16-bit receive counter's data enters into the Din pin. This simultaneous entry of the transmit and receive counters causes the programming period of the four-pin scheme to be half that of the three-pin scheme (see Figures 14 and 15). While programming Tx/Rx Channel Counter, the ENB pin must be pulsed to provide falling edge to latch the shifted data after the rising edge of the last clock. Maximum data transfer rate is 500 kbps. NOTE 10 ms should be allowed for initial start-up time for the oscillator to allow all registers to clear and enable programming of new register values.
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CONTROL REGISTER IDENTIFIER = 1 CONTROL REGISTER DATA
Din
1 MSB
0
TEST BIT
AUX DATA SELECT
REF OUT 3/ 4
TxPD ENABLE
RxPD ENABLE
REF PD ENABLE LSB
CLK
ENB
NOTE: ENB must be high during the serial transfer.
Figure 8. Programming Format of the Control Register
Table 1. Control Register Function Bits Description
Test Bit Aux Data Select Set to 1 for Tx/Rx channel counter test mode Set to 0 for normal application Set to 1 for both ADin and Din pins inputting the transmit 16-bits data and receive 16-bits data respectively. Set to 0 for normal application interfacing with MCU serial peripheral interface. Does not use ADin pin; tie ADin to VSS. 4 If set to 1, REFout output frequency is equal to OSCout If set to 0, REFout output is OSCout 4. 3.
REFout
3/
TxPD Enable
If set to 1, the transmit counter, transmit phase detector, and the associated circuitry is in power- down mode. Tx PS/fTx is set "High". If set to 1, the receive counter, receive phase detector, and the associated circuitry is in power- down mode. Rx PS/fRx is set "High". If set to 1, both 12-bit and 14-bit reference frequency counters are in power-down mode.
RxPD Enable
Ref PD Enable
Table 2. Control Register Power Down Bits Function
TxPD Enable 0 0 0 0 1 1 1 1 RxPD Enable 0 0 1 1 0 0 1 1 REF PD Enable 0 1 0 1 0 1 0 1 Tx-Channel Counter -- -- -- -- Power Down Power Down Power Down Power Down Rx-Channel Counter -- -- Power Down Power Down -- -- Power Down Power Down Reference Frequency Counter -- Power Down -- Power Down -- Power Down -- Power Down
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REFERENCE FREQUENCY COUNTER IDENTIFIER = 0
REFERENCE FREQUENCY SELECT
REFERENCE FREQUENCY COUNTER DIVIDE RATIO
REFERENCE FREQUENCY SELECT
AUX REFERENCE FREQUENCY COUNTER DIVIDE RATIO
Din
0
AUX Tx-0 Rx-0 REF ENABLE SELECT SELECT
12-BITS REF FREQ DATA
fR1 S1
fR1 S2
14-BITS AUX REF FREQ DATA
CLK
ENB
NOTE: ENB must be high during the serial transfer.
Figure 9. Programming Format of the Auxiliary/Reference Frequency Counters
Din MCU USING SERIAL PERIPHERAL INTERFACE PORT UNIVERSAL PLL AUX DATA BIT = 0 ENB
CLK
Figure 10. MCU Interface Using SPI
ADin Din CLK
MCU USING NORMAL I/O PORT
UNIVERSAL PLL AUX DATA BIT = 1
ENB
Figure 11. MCU Interface Using Normal I/O Ports with Both Din and ADin for Faster Programming Time
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CONTROL REGISTER IDENTIFIER = 1
CONTROL REGISTER DATA
Din
1 MSB
0
TEST BIT
AUX DATA SELECT
REF OUT 3/ 4
TxPD ENABLE
RxPD ENABLE
REF PD ENABLE LSB
AUX DATA SELECT = 0 CLK
ENB
NOTE: ENB must be high during the serial transfer.
Figure 12. Programming Format for Control Register (3-Pin Interfacing Scheme)
Din
16-BIT Tx COUNTER DIVIDE RATIO
16-BIT Rx COUNTER DIVIDE RATIO
CLK
LAST CLOCK
ENB
NOTE: ENB must be low during the serial transfer.
Figure 13. Programming Format for Transmit and Receive Counters (3-Pin Interfacing Scheme)
CONTROL REGISTER IDENTIFIER = 1
CONTROL REGISTER DATA
Din
1 MSB
0
TEST BIT
AUX DATA SELECT
REF OUT 3/ 4
TxPD ENABLE
RxPD ENABLE
REF PD ENABLE LSB
AUX DATA SELECT = 1
CLK
ENB
NOTE: ENB must be high during the serial transfer.
Figure 14. Programming Format for Control Register (4-Pin Interfacing Scheme)
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ADin
16-BIT Tx COUNTER DIVDE RATIO
Din
16-BIT Rx COUNTER DIVIDE RATIO
CLK
LAST CLOCK
ENB
NOTE: ENB must be low during the serial transfer.
Figure 15. Programming Format for Transmit and Receive Counters (4-Pin Interfacing Scheme)
Table 3. Global CT-1 Reference Frequency Setting vs Channel Frequencies
Country U.S.A. France Spain Australia U.K. New Zealand Channels Frequency 46/49 MHz (10, 15, 25 Channels) 26/41 MHz 31/41 MHz 30/39 MHz 1.7/47 MHz 1.7/34/40 MHz fR1 5.0 kHz 6.25 kHz/12.5 kHz 5.0 kHz 5.0 kHz 6.25 kHz 6.25 kHz fR2 -- -- -- -- 1.0 kHz 1.0 kHz
REFERENCE FREQUENCY SELECTION AND PROGRAMMING Figure 16 shows the bit function of the reference frequency programming word. The user can either select the "fixed" reference frequency for all channels accordingly or provide a specific reference frequency for a particular channel by using two reference frequency counters (e.g., for an application in France, the base set transmit channel common fixed reference frequency is 6.25 kHz or 12.5 kHz). (See Table 3 and Figure 6 for reference frequencies for various countries.) However, transmit channels 6, 8, and 14 can be set to 25 kHz, and channel 8 reference frequency can be set to 50 kHz. But this reference frequency may not be applied to the receiving side; therefore, the receiving side reference frequency must be generated by another reference frequency counter. The higher the reference frequency, the better the phase noise performance and faster the lock time, but the PLL consumes more current if both reference frequency counters are in operation. In general, the 12-bit reference frequency counter plus the / 4
and / 25 module can offer all the reference frequencies for global CT-1 transmit and receive channel requirements. Users can select their own reference frequency by introducing the additional 14-bit auxiliary reference frequency counter. Again, the 14-bit auxiliary reference frequency counter can be shut down by the auxiliary reference enable bit in the reference counter programming word by setting the bit to 0. At this state, the fR2 is automatically connected to point C (the /25 block output), and fR1 can be connected to point A or B by setting the fR1-S1 and fR1-S2 bits in the reference counter program word. The 14-bit auxiliary reference frequency counter data will be in "Don't Care" state. If the 14-bit auxiliary reference frequency counter is enabled (auxiliary reference enable = 1), then fR2 is automatically connected to point D (14-bit counter output), and fR1 can be selected to connect to point A, B, or C, depending on the bit setting of fR1-S1 and fR1-S2. Table 4 and Figure 16 describe the functions of the auxiliary reference enable bit and the fR1-S1 and fR1-S2 bits selection.
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A fR1 OSCin 12-BIT PROGRAMMABLE REFERENCE COUNTER B 4 C 25 14-BIT PROGRAMMABLE AUXILIARY REFERENCE COUNTER D 1 Tx PHASE DETECTOR Tx-0 SELECT TxPDout fR2
OSCout MAXIMUM CRYSTAL FREQUENCY 16.0 MHz
0
LD
1
Rx PHASE DETECTOR Rx-0 SELECT
RxPDout
0 REF FREQUENCY COUNTER IDENTIFIER = 0
REFERENCE FREQUENCY SELECT
REFERENCE FREQUENCY COUNTER
REFERENCE FREQUENCY SELECT
AUXILIARY REFERENCE FREQUENCY COUNTER
Din
0
AUX Tx-0 Rx-0 REF ENABLE SELECT SELECT
12-BITS REF FREQ DATA
fR1 S1
fR1 S2
14-BITS AUX REF FREQ DATA
CLK
ENB
NOTE: ENB must be high during the serial transfer.
Figure 16. Reference Frequency Counter/Selection Programming Mode Table 4. Bit Function and the Reference Frequency Selection Bit Setting of the Reference Frequency Counter Programming Word
AUX REF Enable 0 Auxiliary Reference Frequency Counter Mode 14-Bit Auxiliary Reference Frequency Counter Disable Module Select fR2 C fR1 S1 0 0 1 1 1 14-Bit Auxiliary Reference Frequency Counter Enable fR2 D 0 0 1 1 N/A = Not Applicable fR1 S2 0 1 0 1 0 1 0 1 fR1 Routing N/A fR1 A fR1 B N/A N/A fR1 A fR1 B fR1 C
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POWER SAVING OPERATION This PLL has a programmable power-saving scheme. The transmit and receive counters and the reference frequency counter can be powered down individually by setting the TxPD enable, RxPD enable, and Ref PD enable bits of the control register. The functions of the power down control bits are explained in Table 2 and the programming format is in Figure 8.
The output pins TxPS/fTx and RxPS/fRx output the status of the internal power saving setting. If the bit TxPD enable is set "high" (transmit counter is set to power-down mode), then the TxPS/fTx pin will also output a "high" state. This TxPS/fTx out-put can control an external power switch to switch off the transmitter, as shown in Figure 17. This scheme can be applied to the RxPS/fRx output to control the receiver power saving operation as required.
POWER SUPPLY
UNIVERSAL DUAL PLL VDD TxPS/fTx Q Tx POWER-DOWN ENABLE FLAG
POWER SWITCH FOR TRANSMITTER Tx DIVIDER CHAIN COUNTER, PHASE DETECTOR
Tx POWER AMP
VDD RxPS/fRx Q Rx POWER-DOWN ENABLE FLAG
TO CONTROL THE RECEIVER POWER SWITCH
Rx DIVIDER CHAIN COUNTER, PHASE DETECTOR
Figure 17. TxPS/fTx and RxPS/fRx Outputs to Control Power Switches of the Transmitter and the Receiver
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Tx/Rx CHANNEL COUNTER TEST In normal applications, the TxPS/fTx and the RxPS/fRx output pins indicate the power saving mode status. However, the user can examine the Tx and Rx channel counter outputs by setting the Test bit in the control register to 1. The final value
of the transmit-channel counter and the receive-channel counter multiplex out to TxPS/fTx and RxPS/fRx respectively. The user can verify the divided-down output waveform associated with the RF input level in the PLL circuitry implementation (Figure 18).
fin-T
16-BIT Tx PROGRAMMABLE CHANNELS COUNTER
fTx TxPS / fTx
TxPS IF TEST BIT IS SET TO 1, THE fTx AND fRx ARE MUXED OUT AT PINS TxPS/fTx AND RxPS/fRx, RESPECTIVELY, FOR Rx/Tx CHANNEL COUNTER TEST.
CONTROL REGISTER IDENTIFIER = 1 CONTROL REGISTER
Din
1
0
TEST BIT
AUX DATA SELECT
REF OUT 3/ 4
TxPD ENABLE
RxPD ENABLE
REF PD ENABLE
fin-R
16-BIT Rx PROGRAMMABLE CHANNELS COUNTER
RxPS / fRx
fRx
RxPS
Figure 18. RF Buffer Sensitivity
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Table 5. France CT-1 Base Set Frequency
Channel Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Tx Channel Frequency (MHz) 26.4875 26.4750 26.4625 26.4500 26.4375 26.4250 26.4125 26.4000 26.3875 26.3750 26.3625 26.3500 26.3375 26.3250 26.3125 Tx Counter Value (Ref. Freq. = 6.25 kHz) 4238 4236 4234 4232 4230 4228 4226 4224 4222 4220 4218 4216 4214 4212 4210 fin-R Input Frequency (MHz) [1st IF = 10.7 MHz] 30.7875 30.7750 30.7625 30.7500 30.7375 30.7250 30.7125 30.7000 30.6875 30.6750 30.6625 30.6500 30.6375 30.6250 30.6125 Rx Counter Value (Ref. Freq. = 6.25 kHz) 4926 4924 4922 4920 4918 4916 4914 4912 4910 4908 4906 4904 4902 4900 4898
Table 6. France CT-1 Handset Frequency
Channel Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Tx Channel Frequency (MHz) 41.4875 41.4750 41.4625 41.4500 41.4375 41.4250 41.4125 41.4000 41.3875 41.3750 41.3625 41.3500 41.3375 41.3250 41.3125 Tx Counter Value (Ref. Freq. = 6.25 kHz) 6638 6636 6634 6632 6630 6628 6626 6624 6622 6620 6618 6616 6614 6612 6610 fin-R Input Frequency (MHz) [1st IF = 10.7 MHz] 37.1875 37.1750 37.1625 37.1500 37.1375 37.1250 37.1125 37.1000 37.0875 37.0750 37.0625 37.0500 37.0375 37.0250 37.0125 Rx Counter Value (Ref. Freq. = 6.25 kHz) 5950 5948 5946 5944 5942 5940 5938 5936 5934 5932 5930 5928 5926 5924 5922
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Table 7. Spain CT-1 Base Set Frequency
Channel Number 1 2 3 4 5 6 7 8 9 10 11 12 Tx Channel Frequency (MHz) 31.0250 31.0500 31.0750 31.1000 31.1250 31.1500 31.1750 31.2000 31.2500 31.2750 31.3000 31.3250 Tx Counter Value (Ref. Freq. = 5.00 kHz) 6205 6210 6215 6220 6225 6230 6235 6240 6250 6255 6260 6265 fin-R Input Frequency (MHz) [1st IF = 10.695 MHz] 29.2300 29.2550 29.2800 29.3050 29.3300 29.3550 29.3800 29.4050 29.4550 29.4800 29.5050 29.5300 Rx Counter Value (Ref. Freq. = 5.00 kHz) 5846 5851 5856 5861 5866 5871 5876 5881 5891 5896 5901 5906
Table 8. Spain CT-1 Handset Frequency
Channel Number 1 2 3 4 5 6 7 8 9 10 11 12 Tx Channel Frequency (MHz) 39.9250 39.9500 39.9750 40.0000 40.0250 40.0500 40.0750 40.1000 40.1500 40.1750 40.2000 40.2250 Tx Counter Value (Ref. Freq. = 5.00 kHz) 7985 7990 7995 8000 8005 8010 8015 8020 8030 8035 8040 8045 fin-R Input Frequency (MHz) [1st IF = 10.7 MHz] 20.3300 20.3550 20.3800 20.4050 20.4300 20.4550 20.4800 20.5050 20.5550 20.5800 20.6050 20.6300 Rx Counter Value (Ref. Freq. = 5.00 kHz) 4066 4071 4076 4081 4086 4091 4096 4101 4111 4116 4121 4126
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Table 9. New Zealand CT-1 Base Set Frequency
Channel Number 1 2 3 4 5 6 7 8 9 10 Tx Channel Frequency (MHz) 1.7820 1.7620 1.7420 1.7220 1.7020 34.3500 34.3625 34.3750 34.3875 34.4000 fin-R Input Frequency (MHz) [1st IF = 10.7 MHz] 29.7625 29.7500 Ref Freq = 1.0 kHz 29.7375 29.7250 29.7125 29.7000 29.6875 Ref Freq = 6.25 kHz 29.6750 29.6625 29.6500 Rx Counter Value (Ref. Freq. = 6.25 kHz) 4762 4760 4758 4756 4754 4752 4750 4748 4746 4744
Tx Counter Value 1782 1762 1742 1722 1702 5496 5498 5500 5502 5504
Table 10. New Zealand CT-1 Handset Frequency
Channel Number 1 2 3 4 5 6 7 8 9 10 Tx Channel Frequency (MHz) 40.4625 40.4500 40.4375 40.4250 40.4125 40.4000 40.3875 40.3750 40.3625 40.3500 Tx Counter Value (Ref. Freq. = 6.25 kHz) 6474 6472 6470 6468 6466 6464 6462 6460 6458 6456 fin-R Input Frequency (MHz) 2.2370 2.2170 2.1970 2.1770 2.1570 23.6500 23.6625 23.6750 23.6875 23.7000 Ref Freq = 10.7 kHz Ref Freq = 455 kHz
Rx Counter Value 2237 2217 2197 2177 2157 3784 3786 3788 3790 3792 Ref Freq = 6.25 kHz Ref Freq = 1.0 kHz
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ML145162
LANSDALE Semiconductor, Inc.
Table 11. Australia CT-1 Base Set Frequency
Channel Number 1 2 3 4 5 6 7 8 9 10 Tx Channel Frequency (MHz) 30.0750 30.1250 30.1750 30.2250 30.2750 30.1000 30.1500 30.2000 30.2500 30.3000 Tx Counter Value (Ref. Freq. = 5.00 kHz) 6015 6025 6035 6045 6055 6020 6030 6040 6050 6060 fin-R Input Frequency (MHz) [1st IF = 10.695 MHz] 29.0800 29.1300 29.1800 29.2300 29.2800 29.1050 29.1550 29.2050 29.2550 29.3050 Rx Counter Value (Ref. Freq. = 5.00 kHz) 5816 5826 5836 5846 5856 5821 5831 5841 5851 5861
Table 12. Australia CT-1 Handset Frequency
Channel Number 1 2 3 4 5 6 7 8 9 10 Tx Channel Frequency (MHz) 39.7750 39.8250 39.8750 39.9250 39.9750 39.8000 39.8500 39.9000 39.9500 40.0000 Tx Counter Value (Ref. Freq. = 5.00 kHz) 7955 7965 7975 7985 7995 7960 7970 7980 7990 8000 fin-R Input Frequency (MHz) [1st IF = 10.7 MHz] 19.3800 19.4300 19.4800 19.5300 19.5800 19.4050 19.4550 19.5050 19.5550 19.6050 Rx Counter Value (Ref. Freq. = 5.00 kHz) 3876 3886 3896 3906 3916 3881 3891 3901 3911 3921
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ML145162
LANSDALE Semiconductor, Inc.
Table 13. U.K. CT-1 Base Set Frequency
Channel Number 1 2 3 4 5 6 7 8 Tx Channel Frequency (MHz) 1.6420 1.6620 1.6820 1.7020 1.7220 1.7420 1.7620 1.7820 Tx Counter Value (Ref. Freq. = 1.00 kHz) 1642 1662 1682 1702 1722 1742 1762 1782 fin-R Input Frequency (MHz) [1st IF = 10.7 MHz] 36.75625 36.76875 36.78125 36.79375 36.80625 36.81875 36.83125 36.84375 Rx Counter Value (Ref. Freq. = 6.25 kHz) 5881 5883 5885 5887 5889 5891 5893 5895
Table 14. U.K. CT-1 Handset Frequency
Channel Number 1 2 3 4 5 6 7 8 Tx Channel Frequency (MHz) 47.45625 47.46875 47.48125 47.49375 47.50625 47.51875 47.53125 47.54375 Tx Counter Value (Ref. Freq. = 6.25 kHz) 7593 7595 7597 7599 7601 7603 7605 7607 fin-R Input Frequency (MHz) [1st IF = 455 kHz] 2.097 2.117 2.137 2.157 2.177 2.197 2.217 2.237 Rx Counter Value (Ref. Freq. = 1.00 kHz) 2097 2117 2137 2157 2177 2197 2217 2237
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ML145162
LANSDALE Semiconductor, Inc.
Table 15. U.S.A. (10 Channels) CT-1 Base Set Frequency
Channel Number 1 2 3 4 5 6 7 8 9 10 Tx Channel Frequency (MHz) 46.610 46.630 46.670 46.710 46.730 46.770 46.830 46.870 46.930 46.970 Tx Counter Value (Ref. Freq. = 5.00 kHz) 9322 9326 9334 9342 9346 9354 9366 9374 9386 9394 fin-R Input Frequency (MHz) [1st IF = 10.695 MHz] 38.975 38.150 38.165 39.075 39.180 39.135 39.195 39.235 39.295 39.275 Rx Counter Value (Ref. Freq. = 5.00 kHz) 7795 7830 7833 7815 7836 7827 7839 7847 7859 7855
Table 16. U.S.A. (10 Channels) CT-1 Handset Frequency
Channel Number 1 2 3 4 5 6 7 8 9 10 Tx Channel Frequency (MHz) 49.670 49.845 49.860 49.770 49.875 49.830 49.890 49.930 49.990 49.970 Tx Counter Value (Ref. Freq. = 5.00 kHz) 9934 9969 9972 9954 9975 9966 9978 9986 9998 9994 fin-R Input Frequency (MHz) [1st IF = 10.7 MHz] 35.915 35.935 35.975 36.015 36.035 36.075 36.135 36.175 36.235 36.275 Rx Counter Value (Ref. Freq. = 5.00 kHz) 7183 7187 7195 7203 7207 7215 7227 7235 7247 7255
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ML145162
LANSDALE Semiconductor, Inc.
Table 17. U.S.A. (25 Channels) CT-1 Base Set Frequency
Channel Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Tx Channel Frequency (MHz) 43.72 43.74 43.82 43.84 43.92 43.96 44.12 44.16 44.18 44.20 44.32 44.36 44.40 44.46 44.48 46.61 46.63 46.67 46.71 46.73 46.77 46.83 46.87 46.93 46.97 Tx Counter Value (Ref. Freq. = 5.00 kHz) 8744 8748 8764 8768 8784 8788 8824 8832 8836 8840 8864 8872 8880 8892 8896 9322 9326 9334 9342 9346 9354 9366 9374 9386 9394 fin-R Input Frequency (MHz) [1st IF = 10.7 MHz] 38.06 38.14 38.16 38.22 38.32 38.38 38.40 38.46 38.50 38.54 38.58 38.66 38.70 38.76 38.80 38.97 39.145 39.16 39.07 39.175 39.13 39.19 39.23 39.29 39.27 Rx Counter Value (Ref. Freq. = 5.00 kHz) 7612 7628 7632 7644 7664 7676 7680 7692 7700 7708 7716 7732 7740 7752 7760 7794 7829 7832 7814 7835 7826 7838 7846 7858 7854
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ML145162
LANSDALE Semiconductor, Inc.
Table 18. U.S.A. (25 Channels) CT-1 Handset Frequency
Channel Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Tx Channel Frequency (MHz) 48.76 48.84 48.86 48.92 49.02 49.08 49.10 49.16 49.20 49.24 49.28 49.36 49.40 49.46 49.50 49.67 49.845 49.86 49.77 49.875 49.83 49.89 49.93 49.99 49.97 Tx Counter Value (Ref. Freq. = 5.00 kHz) 9752 9768 9772 9748 9804 9816 9820 9832 9840 9848 9856 9872 9880 9892 9900 9934 9969 9972 9954 9975 9966 9978 9986 9998 9994 fin-R Input Frequency (MHz) [1st IF = 10.7 MHz] 33.02 33.04 33.12 33.14 33.22 33.26 33.42 33.46 33.48 33.50 33.62 33.66 33.70 33.76 33.78 33.91 33.93 33.97 36.01 36.03 36.07 36.13 36.17 36.23 36.27 Rx Counter Value (Ref. Freq. = 5.00 kHz) 6604 6608 6624 6628 6644 6652 6684 6692 6696 6700 6724 6732 6740 6752 6756 7182 7186 7194 7202 7206 7214 7226 7234 7246 7254
Table 19. Korea CT-1 Base Set Frequency
Channel Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Tx Channel Frequency (MHz) 46.610 46.630 46.670 46.710 46.730 46.770 46.830 46.870 46.930 46.970 46.510 46.530 46.550 46.570 46.590 Tx Counter Value (Ref. Freq. = 5.00 kHz) 9322 9326 9334 9342 9346 9354 9366 9374 9386 9394 9302 9306 9310 9314 9318 fin-R Input Frequency (MHz) [1st IF = 10.695 MHz] 38.975 38.150 38.165 39.075 39.180 39.135 39.195 39.235 39.295 39.275 39.000 39.015 39.030 39.045 39.060 Rx Counter Value (Ref. Freq. = 5.00 kHz) 7795 7830 7833 7815 7836 7827 7839 7847 7859 7855 7800 7803 7806 7809 7812
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ML145162
LANSDALE Semiconductor, Inc.
Table 20. Korea CT-1 Handset Frequency
Channel Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Tx Channel Frequency (MHz) 49.670 49.845 49.860 49.770 49.875 49.830 49.890 49.930 49.990 49.970 49.695 49.710 49.725 49.740 49.755 Tx Counter Value (Ref. Freq. = 5.00 kHz) 9934 9969 9972 9954 9975 9966 9978 9986 9998 9994 9939 9942 9945 9948 9951 fin-R Input Frequency (MHz) [1st IF = 10.7 MHz] 35.915 35.935 35.975 36.015 36.035 36.075 36.135 36.175 36.235 36.275 35.815 35.835 35.855 35.875 35.895 Rx Counter Value (Ref. Freq. = 5.00 kHz) 7183 7187 7195 7203 7207 7215 7227 7235 7247 7255 7163 7167 7171 7175 7179
Table 21. China CT-1 Base Set Frequency
Channel Number 1 2 3 4 5 6 7 8 9 10 Tx Channel Frequency (MHz) 45.250 45.275 45.300 45.325 45.350 45.375 45.400 45.425 45.450 45.475 Tx Counter Value (Ref. Freq. = 5.00 kHz) 9050 9055 9060 9065 9070 9075 9080 9085 9090 9095 fin-R Input Frequency (MHz) [1st IF = 10.7 MHz] 37.550 37.575 37.600 37.625 37.650 37.675 37.700 37.725 37.750 37.775 Rx Counter Value (Ref. Freq. = 5.00 kHz) 7510 7515 7520 7525 7530 7535 7540 7545 7550 7555
Table 22. China CT-1 Handset Frequency
Channel Number 1 2 3 4 5 6 7 8 9 10 Tx Channel Frequency (MHz) 48.250 48.275 48.300 48.325 48.350 48.375 48.400 48.425 48.450 48.475 Tx Counter Value (Ref. Freq. = 5.00 kHz) 9650 9655 9660 9665 9670 9675 9680 9685 9690 9695 fin-R Input Frequency (MHz) [1st IF = 10.7 MHz] 34.550 34.575 34.600 34.625 34.650 34.675 34.700 34.725 34.750 34.775 Rx Counter Value (Ref. Freq. = 5.00 kHz) 6910 6915 6920 6925 6930 6935 6940 6945 6950 6955
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ML145162 OUTLINE DIMENSIONS
P DIP 16 = EP (ML145162EP) PLASTIC DIP CASE 648-08 -A-
16 9
LANSDALE Semiconductor, Inc.
B
1 8
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0 10 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0 10 0.51 1.01
F S
C
L
-T- H G D
16 PL
SEATING PLANE
K
J TA
M
M
0.25 (0.010)
M
-A-
SOG 16 = -5P (ML145162-5P) SOG PACKAGE CASE 751B-05
9
16
-B-
1 8
P
8 PL
0.25 (0.010)
M
B
S
G F
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0 7 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0 7 0.229 0.244 0.010 0.019
K C -T-
SEATING PLANE
R
X 45
M D
16 PL M
J
0.25 (0.010)
TB
S
A
S
DIM A B C D F G J K M P R
Lansdale Semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Lansdale does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. "Typical" parameters which may be provided in Lansdale data sheets and/or specifications can vary in different applications, and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by the customer's technical experts. Lansdale Semiconductor is a registered trademark of Lansdale Semiconductor, Inc.
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